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Table of Contents
Block Statements
Built-in Primitives
Case Statement
Continuous Assignments
Conversion Functions
Compiler Directives
Conditional Operator
Disable Statement
Display Tasks
Edge Sensitive Path
Expression Bit Length
File I/O Functions
If Statement
Integer Constants
Intra-assignment Timing Controls
Loop Statements
min:typ:max Delays
Module Declaration
Module Instantiation
Module Path Declaration
Module Path Polarity
Net Data Types
PLA Modeling Tasks
Probabilistic Distribution Functions
Procedural Assignments
Procedural Continuous Assignments
Procedural Timing Control
Range Specification
Real Constants
Register Data Types
Simulation Control Tasks
Simulation Time Functions
Specify Block
State Dependent Path
Stochastic Analysis Tasks
Structured Procedures
Timescale System Tasks
Timing Check Tasks
UDP Declaration
UDP Instantiation
UDP State Table
Value Change Dump (VCD) File

State Dependent Path

Formal Definition

State Dependent Path is a path that occurs only when the condition is met.

Simplified Syntax

if (condition) simple_module_path;

if (condition) edge_sensitive_path;

ifnone simple_module_path;


Generally, state dependent path is comprised of three parts. A condition that enables the module path, a module path description and a delay that applies to the module path.

The condition is an expression using scalars or vectors of any type. It can also be part-selects or bit-selects of a vector. Constant numbers and specparams can be used in the condition expression. The result of the conditional expression can be one bit or multiple bits. If it is more than one bit, the least significant bit represents the result.

When no edge transition is specified for the inputs, it is called the simple state-dependent path. Example 1 shows the simple-dependent path.

If any edge transition is specified for the input, then it is called an edge-sensitive state-dependent path. Different delays can be used to the same path if the following rules are followed:

  • A declaration must be unique and should use an edge or a conditional expression or both.

  • The port for which the delay is specified must be referenced in exactly the same way. You cannot mix part select, bit-select and complete ports.


Example 1

module example1 (cond, in_1, in_2, out);
input in_1, in_2, cond ;
output out ;
and (out, in_1, in_2) ;
  specparam TRise1 = 5,
  TFall1 = 5,
  TRise2 = 7,
  TFall2 = 7;
  if (cond) ( in_1, in_2 *> out ) = (TRise1, TFall1);
  if (~cond) ( in_1, in_2 *> out ) = (TRise2, TFall2);

If a conditional expression 'cond' is true, TRise1 and TFall1 will be assigned to a path as delays. When the conditional expression 'cond' is false, TRise2 and TFall2 will be used as the path delays.

Important Notes

  • When a conditional expression evaluates to x or z, it should be treated as true.


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