Procedural Timing Control
The procedural timing control is used to determine when statements
should be executed.
Event type declaration:
wait (expression) statement
The Verilog HDL has two types of timing controls: delay control (Example
1) and event control (Example
The delay control specifies the time between encountering and
executing the statement. The delay control can be specified as a
simple delay and as min:typ:max delay.
The named event (Example 3)
is a special data type that does not hold any value. The event can be
triggered using special characters ->
followed by an event identifier. Any occurrence of an event trigger
can be noticed using an event control statement.
An event control specifies the event that is required to resume
execution of a statement. Event can be one of the following:
Change of a signal value
Positive or negative edge occurred on signal (posedge,
List of above-mentioned events (separated by or
- event or operator)
A posedge is any transition
from 0, x, and z to 1, and from 0 to z or x.
A negedge is any transition
from 1, x, and z to 0, and from 1 to z or x.
The wait statement (Example
4) will suspend execution of all statements until the expression
The next statement will be executed after 10 time units.
#10 a = 5;
Assignment to a variable will be delayed by 10 time units.
Delay control with min:typ:max delay value.
#(5:3:7) a = 5;
Assignment to a variable delayed by min:typ:max delay value.
@ready a = a + 1;
The 'a' variable will be incremented by 1 when a change occurs on the
@(posedge clk) q = d;
The 'd' variable will be assigned to 'q' on the positive edge of clk.
@(a or b or
c or d)
y = (a | b) & (~c ^ d);
A new value will be assigned to the 'y' variable when a change occurs
on any of the variables a, b, c, or d.
Example of event triggering.
always @e d = 0;
Example of waiting for an event.
i = i + 1;
This sequence of statements will wait until 'a' becomes 1, and then
the next statement will be executed. Next, execution will be
suspended until 'a' becomes 0.