Verilog Online Help Prev Page Prev Page
Table of Contents
Block Statements
Built-in Primitives
Case Statement
Continuous Assignments
Conversion Functions
Compiler Directives
Conditional Operator
Disable Statement
Display Tasks
Edge Sensitive Path
Expression Bit Length
File I/O Functions
If Statement
Integer Constants
Intra-assignment Timing Controls
Loop Statements
min:typ:max Delays
Module Declaration
Module Instantiation
Module Path Declaration
Module Path Polarity
Net Data Types
PLA Modeling Tasks
Probabilistic Distribution Functions
Procedural Assignments
Procedural Continuous Assignments
Procedural Timing Control
Range Specification
Real Constants
Register Data Types
Simulation Control Tasks
Simulation Time Functions
Specify Block
State Dependent Path
Stochastic Analysis Tasks
Structured Procedures
Timescale System Tasks
Timing Check Tasks
UDP Declaration
UDP Instantiation
UDP State Table
Value Change Dump (VCD) File


Formal Definition

Memories are arrays of registers.

Simplified Syntax

reg memory_width memory_identifier memory_depth;

integer memory_identifier memory_length;

time memory_identifier memory_length;


Memories can be declared only for reg, integer and time data types. Depth of memory should be declared by specifying a range following the memory identifier (Example 1). Registers and memories can be declared in the same line (Example 2). Elements of memory type can be accessed by memory index (Example 3). An assignment to a memory identifier without specified memory index is illegal. Bit-selects and part-selects on memory elements are not allowed. If access to individual bits of memory is needed, then a word containing that bit should be assigned to a register with the same width. All operations should then be done on this register and the result should be assigned back to the memory word (Example 5). Memory words can be accessed individually, but bit-select and part-select operations cannot be done on memories or memory words directly.

Vector declaration and memory declaration are not the same. If a variable is declared as a vector, all bits can be assigned a value in one statement. If a variable is declared as memory then a value to each element should be assigned separately (Example 4).


Example 1

reg [7:0] mem[1023:0];
integer i_mem[8:1];

The 'mem' variable is a memory that contains 1024 8-bit words.

The 'i_mem' variable has 8 words (each word is an integer register).

Example 2

reg [3:0] mem[255:0], r;

This line a declares 4-bit register 'r' and memory 'mem', which contains 256 4-bit words.

Example 3

reg [7:0] mem [3:0], r;
mem[0] = 7;
r = mem[3];
mem[1] = r;

Example 4

reg [7:0] vect;
reg array[7:0];
vect = 8'b11001010;
array[7] = 1'b1;
array[6] = 1'b1;
array[5] = 1'b0;
array[4] = 1'b0;
array[3] = 1'b1;
array[2] = 1'b0;
array[1] = 1'b1;
array[0] = 1'b0;

If the variable is declared as a vector (variable vect), then the new value can be assigned to all bits at the same time. If a variable is declared as a memory (variable array) type, then the new value should be assigned to each element of memory separately.

Example 5

reg [7:0] mem[255:0], r;
r = mem[135];
r[3:1] = 3'b100;
mem[135] = r;

This example shows how to access particular bits of memory.

Important Notes

  • Memories can be declared only for reg, integer and time registers types.

  • Bit-selects and part-selects on memory elements are prohibited.


Powered by IXwebhosting