Prev Page Next Page


Formal Definition

Parameters are constants typically used to specify the width of variables and time delays.

Simplified Syntax

parameter identifier = constant_expression ,

identifier = constant_expression ;

defparam hierarchical_path = constant_expression ;


In Verilog HDL, parameters are constants and do not belong to any other data type such as net or register data types.

A constant expression refers to a constant number or a previously defined parameter (see Example 1). You are not allowed to modify parameter values at runtime, but you can modify a parameter value using the defparam statement. The defparam statement can modify parameters only at the time of compilation. Parameter values can also be modified using #delay specification with module instantiation.

In Verilog there are two ways to override a module parameter value during a module instantiation. The first method is by using the defparam keyword and the second method is called module instance parameter value assignment.

After the defparam keyword, the hierarchical path to the parameter is specified along with the new value of the parameter. In this case, the new value should be a constant expression (see Example 2). If the right-hand side expression references any parameters it should be declared within the module where defparam is invoked (see Example 3).

The module instance parameter value assignment method looks like an assignment of delay to gate instance (see Example 4). This method overrides parameters inside instantiated modules, in the order, that they appear in the module. Using this format, parameters cannot be skipped.

Constant expressions can contain previously declared parameters. When changes are detected on the previously declared parameters, all parameters that depend on this value are automatically updated (see Example 5).


Example 1

parameter lsb = 7 ;
parameter size = 8 ,
word = 32 ;
parameter number = 3.92,
frequency = 100 ;
parameter clk_cycle = frequency / 2 ;

Example 2

module my_module (Clk, D, Q) ;
parameter width = 2,
delay = 10 ;
input [width - 1 : 0] D ;
input Clk ;
output [width : 0] Q ;
assign #delay Q = D;

Example 3

module top;
reg Clk ;
reg [7:0] D ;
wire [7:0] Q ;
my_module inst_1(Clk, D, Q) ;
module override ;
defparam top.inst_1.width = 7 ;

Example 4

module top;
reg Clk ;
reg [7:0] D ;
wire [7:0] Q ;
my_module #(7, 25) inst_1(Clk, D, Q) ;

Example 5

parameter foo = 4;
parameter data = foo / 10 ;

When 'foo' changes, 'data' is automatically updated.

Important Notes


Prev Page Next Page
Powered by IXwebhosting